This invention relates to a clock and data recovery circuit and clock control method thereof.
FIG. 8 is a diagram illustrating the structure of a clock and data recovery circuit according to the prior art. As shown in FIG. 8, the clock and data recovery circuit has a voltage-controlled oscillator (VCO) 51 of a PLL (phase Locked Loop) which generates a multiphase clock (multiphase output) of equally spaced phase differences from a reference clock (Ref CLK) applied thereto. The VCO comprises an analog ring oscillator, which is composed by an odd-number of inverter circuits connected into a ring-shaped configuration. A multiphase clock of equally spaced phase differences is extracted differentially from the outputs of differential inverting circuits constructing the ring oscillator. The clock and data recovery circuit has a plurality of flip-flops 52 (F/F1 to F/F8), which have data input terminals for receiving the input data DATA commonly and clock input terminals for receiving respective clock signals of the multiphase clock output from the VCO 51. The flip-flop 52 samples and outputs the input data DATA at a rising or falling edge of the clock signal fed to the clock input terminal.
This clock and data recovery circuit has a counter 53, which receives the data output from each of the plurality of flip-flops 52 (F/F1 to F/F8), and which counts the logic value of the data up and down, and a filter 55 which performs time-averaging of the output of the counter 53 over a predetermined time constant. The output voltage of the filter 55 is supplied as the control voltage of the VCO 51. Some or all of the outputs of the flip-flops 52 and one phase of the clock output from the VCO 51 are output as data and a clock signal. The outputs of the plurality of flip-flops (F/F1 to F/F8) are the result of sampling the data DATA by clock signals phase-shifted in small increments. The sampled waveform obtained is the result of sampling the data DATA at a frequency that is eight times the frequency of the reference clock signal. The timing of the clock signal of a flip-flop for which the output value does not agree with the output value of the neighboring flip-flop is the transition point of the data DATA (this point is also referred to as the xe2x80x9cdata changeover portionxe2x80x9d).
If the clock signal lags with respect to the data transition time point (i.e., if latch timing is lagging), the value of the counter 53 is counted up to advance the phase of the clock signal. If the clock leads the data transition time point (i.e., if the latch timing is leading), the value of the counter 53 is counted down to delay the phase of the clock signal. It should be noted that the counter 53 may comprise a charge pump (CP) for charging a capacitor with a constant current when the output value of each of the plurality of flip-flops (F/F1 to F/F8) is logic xe2x80x9c0xe2x80x9d, and discharging the capacitor with a constant current when the output value is logic xe2x80x9c1xe2x80x9d.
See Reference 1 (ISSCC 1997 pp. 238-239, Alan Fiedler, xe2x80x9cA 1.0625 Gbps Transceiver with 2xc3x97-Oversampling and Transmit Signal Pre-Emphasisxe2x80x9d), which is an example of the clock and data recovery circuit shown in FIG. 8. The clock and data recovery circuit described in Reference 1 has a receiver circuit for recovering a clock and data from input data and outputting resulting data as parallel data. The VCO of a PLL (Phase-Locked Loop) has a 10-delay-stage ring oscillator, and the VCO 20 clock phases provide 2xc3x97 oversampling clock signals to the receiver circuit to recover a clock and data. The receiver circuit locks the VCO to the input data and recovers a clock from an NRZ (Non-Return to Zero) transition. The clock and data recovery circuit described in Reference 1 has a data phase detector that comprises a plurality of high-speed latches and exclusive-OR gates for detecting coincidence/non-coincidence of the high-speed latches. A Latch that samples data bits is clocked by the non-inverted clock signal of the VCO, and a latch that samples the boundary between data bits is clocked by the inverted clock signal of the VCO.
In the conventional circuit shown in FIG. 8, the multiphase clock is generated by the VCO, and a phase interpolator comprising an analog circuit is used as an interpolator.
In the specification of Japanese Patent Application No. 2000-389526 (Japanese Patent Kokai Publication JP-A-P2002-190724A), the present Inventor proposes an arrangement, which is shown in FIG. 9, as a clock and data recovery circuit for facilitating a change in frequency range, facilitating adjustment of characteristics and varying the number of parallel data and clock outputs. This clock and data recovery circuit comprises a plurality of latch circuits 102 to which input data is supplied in common; a phase-shift circuit 101A for generating clock signals, which are phase-shifted from one another, supplied to respective ones of the latch circuits; a counter 103 the count of which is counted up and down based upon the outputs of the plurality of latch circuits 102; a filter 105 for smoothing the output of the counter 103; and a decoder 106 which receives the output of the filter 105 as an input, and decodes the received signal to deliver a signal, which controls the phases of the clock signals, to the phase-shift circuit 101A. On the basis of the output from filter 105, the decoder 106 delays the phases of clock signals CKL1 to CLK8 incrementally whenever the output of counter 103 is incremented.
The clock and data recovery circuit shown in FIG. 9 latches data successively phase by phase using a multiphase clock (eight phases in FIG. 9) the frequency of which is less than that of the data rate. The relationship among the data rate, the frequency of the multiphase clock and the number of phases generally is expressed as follows in approximate fashion:
(data rate)=(frequency of multiphase clock)xc3x97(number of phases)/Kxe2x80x83xe2x80x83(1) 
where K represents a number indicating the number of clock phases by which the width of one bit of data is clocked. In the implementation of FIG. 9, K=2 holds. More specifically, as indicated in the timing diagram of FIG. 11, the data transition time point (the data changeover portion that is the boundary between data bits in the case of the NRZ waveform) and data bit (value of the data) are sampled at two phases.
In the circuit shown in FIG. 9, the results of latching the width of one bit of data at the edges of a plurality of clock signals are compared using the up/down counter 103, thereby detecting the transition time point at which the data changes, phase lead/lag of the data and clock is discriminated, and a signal specifying up (for advancing the clock relative to the data) or down (for delaying the clock relative to the data) is output.
The output of the up/down counter 103 is supplied to the filter circuit 105. The latter operates on the up/down signal and, if the magnitude of count-up, count-down exceeds a fixed value, outputs a signal to the decoder 106 so as to advance or delay the clock phase.
This conventional clock and data recovery circuit is so adapted that the clock signals of the multiphase clock are shifted in unison in the phase-shift circuit 101A.
FIG. 10 is a diagram illustrating the structure of the phase-shift circuit 101A depicted in FIG. 9. As shown in FIG. 10, the phase-shift circuit 101A comprises a switch 110, to which the 8-phase clock is input, for selecting and outputting a plurality of pairs of two mutually adjacent clock signals from the 8-phase clock, and a plurality of interpolators 111 (Int. 1 to Int. 8), which receive plurality of clock pairs output from the switch 110, and output signals in which delay time is stipulated by time obtained by performing interior division of the phase difference between the clock signals of the pair. In a case where the output of the counter 103 is, e.g., eight bits, a signal U of, e.g., the four higher order bits at the output of the decoder 106 is used to control changeover of the switch 110, and a signal S of the four lower order bits at the output of the decoder 106 is used to control the 16-step interpolator 111, which is described below. A 16-step control signal output supplied to the interpolator 111 undergoes a thermometer-type shift. In a case where it is necessary to delay or advance phase with the 16-bit control signal being all xe2x80x9c1xe2x80x9ds or all xe2x80x9c0xe2x80x9ds, the switch 110 is changed over.
The control signal S supplied from the decoder 106 is applied as the common signal to the eight interpolators 111 (Int. 1 to Int. 8). All eight phases of the clock signals are shifted in unison at equal intervals in accordance with the control signal S.
The solid lines in the timing diagram of FIG. 11 represent the original 8-phase clock signals (CLK1 to CLK8) output from the interpolator 111 of FIG. 10, and the dashed lines indicate the 8-phase clock signals after being shifted in phase. As illustrated in FIG. 11, the 8-phase clock signals output from the interpolator 111 are shifted in unison at equal intervals.
An overview of the interpolator 111 shown in FIG. 10 will now be described. FIG. 12A is a diagram illustrating an example of the interpolator structure, and FIG. 12B is a diagram useful in describing the operating principle of the interpolator, namely internal division of phase difference. The interpolator having the structure of FIG. 12A is such that output timing varies in proportion to the driving capability of inverters arranged in parallel. Let N represent the number of inverters INV1 rendered active or inactive by a control signal xcfx86 (N is 16 in the case of a 16-step interpolator), and let N represent the number of inverters INV2 rendered active or inactive by an inverted control signal xcfx86xe2x88x92 obtained by inverting the control signal xcfx86. Each of the parallel-connected inverters INV1 is represented by a single inverter and each of the parallel-connected inverters INV2 is represented by a single inverter in FIG. 12A. The inverter INV1 is such that a switch (not shown) inserted between a CMOS inverter constituting the inverter INV1 and a power-supply path is turned on when the control signal xcfx86 is at the high level, and the inverter INV2 is such that a switch (not shown) inserted between a CMOS inverter constituting the inverter INV2 and a power-supply path is turned on when the control signal xcfx86xe2x88x92 is at the high level. The output terminals of the inverters INV1 and INV2 are tied together and connected to the input terminal of an inverter INV3.
Let C represent the capacitance at the connection node of the output terminals of the inverters INV1 and INV2, N-number of each of which are provided in parallel. When input signals to the inverters INV1 and INV2 are both at the low level, the input node of the inverter INV3 assumes the high power-supply potential (high level). Let CV represent the amount of electric charge to be discharged from the connection node (capacitance C) until the output OUT of the inverter INV3 inverts, and let I represent the discharge current of the inverters INV1, INV2. If n-number (0xe2x89xa6nxe2x89xa6N) of the control signals xcfx86 are placed at the high level and, hence, (Nxe2x88x92n)-number of the inverted control signals xcfx86xe2x88x92 are placed at the high level, then n-number of the inverters INV1 and (Nxe2x88x92n)-number of the inverters INV2 will be activated. The n-number of inverters INV1 discharge the accumulated charge in the capacitance C at a current n I I for a time T at the rising edge of input signal IN1, whereby the electric charge in the capacitance becomes CVxe2x88x92nxc3x97IT, where T represents the time difference (phase difference) between the rising edges of input signals IN1 and IN2. Furthermore, n-number of the inverters INV1 and (Nxe2x88x92n)-number of inverters INV2 discharge the accumulated charge of the capacitance C at a discharge current Nxc3x97I at the rising edge of the input signal IN2 following elapse of the time T from the rising edge of input signal IN1.
Accordingly, the charge becomes (CVxe2x88x92nxc3x97IT)/Nxc3x97I starting from a rising edge of the input signal IN2 for a period of time until the output of the inverter INV3 inverts. In other words, the propagation delay time tpd from the rising edge of input signal IN1 to the rising edge of the output signal of inverter INV3 is given by Equation (2) below.
tpd=T+CV/Nxc3x97Ixe2x88x92nxc3x97T/Nxe2x80x83xe2x80x83(2) 
That is, at n=N, the propagation delay time tpd is minimized and is given by CV/Nxc3x97I (see OUT1 in FIG. 12B). At n=0, the propagation delay time tpd is maximized and is given by T+CV/Nxc3x97I (see OUT3 in FIG. 12B). If n is a value that falls within the range between 1 and Nxe2x88x921, the delay time tpd is stipulated by a time obtained by performing interior division of the phase difference T between the input signals IN1 and IN2 at an internal division ratio 1xe2x88x92x:x (where x=n/N) (see OUT2 in FIG. 12B). In the case of a 16-step interpolator, N=16 holds and the control signal xcfx86 is composed of four bits. Similarly, in the case of a 256-step interpolator, N=256 holds and the control signal xcfx86 is composed of eight bits.
Thus, with the clock and data recovery circuit described above with reference to FIGS. 9 to 12, the control signal supplied from the decoder 106 is applied commonly to the plurality of interpolators 111 in the phase-shift circuit 101A, and all of the multiphase clock signals are shifted in unison at regular intervals at a prescribed phase in dependence upon the control signal.
As a consequence, if the phase of the clock situated in the data changeover portion is shifted in a case where the timing of the data transition point shifts owing to jitter, etc., of the input data, then the phase of the clock of another phase for sampling the value of the data bit also is shifted by the same amount. Hence, there is a greater possibility that data of the correct value will no longer be able to be sampled. For example, if the phase of the data transition point is delayed in a certain cycle owing to jitter of the input data or the like in a case where the data transition and the content of the data bit are being sampled by two phases, then there will also be a case where the phase of the data transition point is advanced in the next cycle (i.e., one cycle is shortened). In a case where the clock for detecting data transition and the clock for sampling the data bit are delayed by the same amount of phase, there will be a case where the data transition region (boundary between the data bits) of a succeeding cycle is sampled as the data bit. Thus, there are instances where the data bit cannot be sampled correctly.
Accordingly, it is an object of the present invention to provide a clock and data recovery circuit and method that make it possible to suppress the effects of jitter components and to sample data accurately.
The above and other objects are attained by a clock and data recovery circuit, in accordance with one aspect of the present invention, which comprises: a phase-shift circuit having a switch, to which a plurality of clock signals (referred to as a xe2x80x9cmultiphase clocksxe2x80x9d) of mutually different phases are supplied, and which selects and outputs a plurality of clock pairs from among the multiphase clocks, and a plurality of interpolators, to which the plurality of clock pairs output from the switch are supplied, for outputting signals in which delay time is stipulated by time obtained by performing interior division of the phase difference between the clock signals of the pair applied thereto; a plurality of latch circuits, to which input data is applied in common, and which sample and output the input data at transition edges of clock signals of mutually shifted phases supplied from the interpolators corresponding to respective ones of the plurality of latch circuits; a phase detecting circuit for detecting and outputting phase, with respect to the clock, of a transition time point of the input data from the outputs of the plurality of latch circuits; a filter for smoothing the output of the phase detecting circuit; and a control circuit for outputting, based upon the output of the filter, a control signal for controlling an interior division ratio of the interpolators of the phase-shift circuit and a control signal for controlling selection of the clock pairs in the switch of the phase-shift circuit. The plurality of interpolators are divided into a plurality of groups in relation to control signals supplied from the control circuit in order to adjust the interior division ratio of the interpolators. The interpolators in the same group are supplied with the same control signal from the control circuit while the interpolators in different groups are supplied separately with respective ones of control signals from the control circuit.
According to another aspect of the present invention, the foregoing object is attained by providing a clock control method of a clock and data recovery circuit having a plurality of latch circuits to which input data is applied in common, the plurality of latch circuits sampling and outputting the input data at transition edges of clock signals of mutually shifted phases supplied to respective ones of the plurality of latch circuits; a phase detecting circuit for detecting and outputting phase, with respect to the clock, of a transition point of the input data from the outputs of the plurality of latch circuits; a filter for smoothing the output of the phase detecting circuit; and a control circuit for controlling the clock phase based upon the output of the filter; a plurality of pairs of clock signals being selected and output from among a plurality of clocks (referred to as a xe2x80x9cmultiphase clocksxe2x80x9d) of mutually different phases by a switch to which the multiphase clocks are supplied, and signals in which delay time is stipulated by time obtained by performing interior division of the phase difference between the clock signals of the pair being output by a plurality of interpolators to which respective ones of the plurality of clock pairs output from the switch are supplied; wherein changeover of selection of the clock pairs in the switch is controlled and interior division ratio of the interpolators is variably set based upon results of decoding the output of the filter, thereby varying phases of clock signals supplied to respective ones of the plurality of latch circuits; the plurality of interpolators are divided into a plurality of groups in relation to control signals supplied from the control circuit; interpolators in the same group are supplied with the same control signal from the control circuit; interpolators in different groups are supplied separately with control signals from the control circuit; and control is executed such that in a case where phases of the clock signals output from one group of interpolators have changed, the phases of clocks output from the interpolators of other groups do not change.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description in conjunction with the accompanying drawings wherein only the preferred embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated of carrying out this invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.